We propose a new multi-valued current-mode signed-digit adder based on negative-differential resistance (NDR) cells. Such cells have previously been implemented using either resonant-tunnelling diodes that are difficult to implement or complex CMOS circuits that emulate the negative-differential resistance of these cells but with limited performances. In this paper, we exploit the concept of the negative impedance region of the ULP (ultra-low power) diode [Dessard V. Sol specific analog techniques for low-noise, high-temperature or ultra-low power circuits. PhD thesis, UCL, Belgium, 2001; Levacq D, et al. Composite ULP diode fabrication, modeling and applications in multi-Vth FD SOI CMOS technology. Solid-State Electron 2004;48(6):1017-25], to design a signed-digit full-adder (SDFA). Signed-digit adders have no carry propagation which means that addition can be made in constant time. Therefore, such adders become more competitive for increasing word lengths. (c) 2005 Elsevier Ltd. All rights reserved.