To design large digital circuits in partially depleted Sol technology, worst and best case propagation delays of digital cells induced by floating body effects must be predicted. In this paper, we propose a time efficient and accurate method based on a smart transistor initialisation technique. This solution allows dividing by a factor 2(n-1) the number of simulations required to completely characterize an n-input gate. This method offers the opportunity to build CAD tools suitable for industrial PD-SOI standard cell libraries characterization. (c) 2005 Published by Elsevier Ltd.