High density data flash memories are essentially used in mobile applications. Flash devices have a small form factor, high storage density and low power consumption. For logic applications FinFET type devices are known to have good scalability down to 10 nm gate length. This device architecture combined with a trapping layer enables memory cells with feature sizes well below 50 rim. To show the scaling potential of SONOS FinFET memories, devices are processed on SOT wafers with fin widths varying from 8 nm to 30 nm and gate lengths scaled down to 20 nm. We discuss three different storage modes of FinFET trapping layer NVM devices: (a) single bit SONOS cell, (b) multilevel SONOS cell and (c) NROM dual bit device. For (a) and (b) program and erase is done with Fowler-Nordheim tunneling and for (c) channel hot electrons are used for programming and hot holes are injected for the erasing of the localized charges. SONOS FinFET memory devices show excellent functionality down to 20 nm channel length. (c) 2005 Elsevier Ltd. All rights reserved.