A 128-bit data operation, 4 Mb e-flash memory has been designed in a 0.18 mu m e-flash process. Read random access to the memory has been decreased down to 20 ns by optimal use of power supply resources and available devices. This memory has two banks of equivalent size allowing read while writing operation for improved application updates, and data management during code execution. Using the pre-fetch buffer concept, in place execution of the code at up to 100 MHz can be obtained in 0.18 mu m on a 32-bit MCU. (c) 2005 Elsevier Ltd. All rights reserved.