While device scaling is entering the sub-20 nm regime, multiple gate transistors are needed to fulfill the ITRS requirements, since they offer a greatly improved electrostatic control of the channel. In this study, after an overview of the existing multi-gate architectures, we show that multi-gate architectures will allow to extend the scaling of CMOS into the sub-10 nm range and we discuss about the technological challenges associated to their fabrication. (c) 2005 Elsevier Ltd. All rights reserved.