Today, the 90 nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22 mn node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, Wafer Bonded Double Gate and SON Gate All Around have been demonstrated with good electrical characteristics at gate lengths of 25-10 nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2 nm gate length. Multi-gate transistors have also been implemented in high density Flash memory cells down to 20 nm. Large V, shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22 nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era. (c) 2006 Elsevier Ltd. All rights reserved.