Double gate fully depleted silicon-on-insulator (DG SOI) is recognized as a possible solution when physical length reduces to nanoscale. In this paper, a new model is presented for DG SOI and single gate SOI (SG SOI) DC, RF and noise modelling. Using this model, the SG SOI and DG SOI analog and noise performance are compared. We have developed for such purpose a noise modeling based on the active line approach and the concept of linear noise theory of two ports for calculating the macroscopic noise sources. The channel is split into elemental sections constituted of a local small signal equivalent circuit associated to an additional microscopic diffusion noise source. DC tunneling gate current expression was implemented. (c) 2006 Elsevier Ltd. All rights reserved.