A significant improvement in device performance was observed for polycrystalline Si thin-film transistors ( poly-Si TFTs ) on stainless steel foil subjected to UV treatment prior to the deposition of the buffer SiO2 layer and gate dielectric film of SiNx/SiO2. This is presumably due to the reduction of the trap-state density in the poly-Si film and at the gate dielectric/poly-Si interface caused by the removal of the organic contamination, which might be induced during the planarization of the rough stainless steel. An excellent subthreshold gate swing ( S ) of 0.38 V/dec, low threshold voltage of -1.4 V, and very low off-current of 3.43 x 10(-14) A/mu m, as well as a high field-effect mobility ( mu(FE) ) of 80.1 cm(2)/V s, were achieved for the p-channel poly-Si TFTs on stainless steel. Thus, it is concluded that poly-Si TFTs on stainless steel can be comparable to those on a conventional glass substrate in terms of their overall device performance, including mu(FE), S, and the off-current. (c) 2007 The Electrochemical Society.