A novel vertical channel dual-nitride-trapping-layer ROM (VDNROM) flash memory with oxide-nitride-oxide-nitride-oxide (ONONO) dielectrics stack is proposed and experimentally demonstrated. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride layers, so it can achieve a four-physical-bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150 degrees C have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high density applications. (C) 2007 Elsevier Ltd. All rights reserved.