Gate dielectric leakage current becomes a serious concern as the gate oxide thickness of metal-oxide-semiconductor field-effect-transistors is less than 3 nm. This thin oxide can conduct significant leakage current by various tunneling mechanisms and degrade circuit performance. A mathematical method of modeling the gate leakage current IG is presented in this work. Both the shallow trench isolation effect and the source-drain extension effect on I-G are included. With suitably chosen transistor dimensions, the parameter extraction can be performed using the devices' mask drawn size, and the troublesome effective device length and width are not necessary in this model. The extracted parameters and their temperature dependence were used to predict IG of devices with other different dimensions. (c) 2007 Elsevier Ltd. All rights reserved.