Charging damage in the fabrication of a micro-and nanoelectronic device is one of the electrical damages during plasma etching and caused basically by a huge difference of the flux velocity distribution between positive ions and electrons toward the wafer to be processed. Beam-like positive ions are accumulated on the bottom of a miniaturized structure during etching. With the evolution of the technology node, charging damage will increase due to several factors, increase of plasma exposure time, decrease of annealing temperature, and narrow process window, etc., caused by the increase of the number of metal layers and the introduction of new materials such as low-k and high-k instead of SiO2. The progress of a top-down nanotechnology depends on the development of in situ diagnostics regarding plasma damage to lower-level elements and on the development of charging-free plasma process. In this paper, in situ charging measurements by using a test chip and negative charge injection to the wafer by optical computerized tomography are first demonstrated. Second, we discuss the characteristics of the charging potential on the bottom of SiO(2)holes during etching in a two-frequency capacitively coupled plasma (2f-CCP), and refer to the procedure to reduce the positive potential by utilizing the negative charge acceleration to the hole bottom under the artificial formation of a double-layer close to the wafer. In addition, the charging's effect on the aspect ratio of the hole and the antenna ratio are discussed. (C) 2007 Elsevier B.V. All rights reserved.