In this work, the influence of Si/ SiO2 interface properties, interface nitridation and remote-plasma- assisted oxidation (RPAO) thickness (< 1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/ SiO2 interface evidenced by less negative V-t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress. (c) 2008 Elsevier B. V. All rights reserved.