Spatial-phase locked electron-beam lithography provides feedback control of electron-beam position by monitoring the signal from a fiducial grid on the substrate. Formerly, a real-time spatial-phase-locking algorithm has been implemented on general purpose microprocessor to provide control for raster-scan system. However, it would be advantageous to provide real-time spatial-phase locking for both vector- and raster-scan systems with accelerated sampling and computational rate demanded by many modern electron-beam lithography tools. In addition, it is desirable for the phase-locking system to be easily parallelizable for multibeam/multicolumn systems. Implementation of vector- and raster-scan spatial-phase locking algorithms on a field-programmable gate array (FPGA) addresses both of these issues. Initial experimental results demonstrate that the FPGA implementation can provide real-time spatial-phase locking effectively at accelerated speed even when the algorithm is performed in the noise limited regime.