This article describes the fabrication process for a silicon single-electron transistor (Si-SET) with tunnel barriers made of thermal silicon dioxide. The fabrication method uses electron-beam lithography, dry etching, and chemical mechanical polishing to make devices with well-defined geometry and good yield. The method introduces chemical mechanical polishing as a key processing technique in the production of nanometer scale features required for the device. The fabricated SETs show charging energies in excess of 20 meV and operating temperatures above liquid nitrogen. All the process steps are fully compatible with the current complementary metal oxide semiconductor (CMOS) technology and combined with the higher operating temperature of the SETs, the fabrication method paves the way for designing of hybrid CMOS-SET architectures. Si-SET can also be a key enabling device for the manufacturable implementation of quantum-dot cellular automata.