A potential distribution analysis of source/drain (SD) regions in sub-30-nm-gate-length metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented as an example of the present status of electron holography analysis. First, the authors describe experimental setups that determine the resolutions of the analysis in practice. They show that specimen preparation artifacts significantly affect the energy resolution and that the artifacts can be reduced by preparing specimens using low-energy back side ion milling. Second, they describe the SD potential analysis in sub-30-nm-gate-length MOSFETs.