Results from process simulations of the stress memorization technique (SMT) for nanoscale n-channel metal-oxide-semiconductor field effect transistors (n MOSFETs) are presented. The spatial distribution of stress components within the device was computed for (i) different germanium doses in the preamorphization implant step, (ii) different peak anneal temperatures in spike annealing, and (iii) different tensile stresses of the capping layer. The effect of the dielectric spacer is considered. During the spike anneal, stress is enhanced in the dielectric spacer due to the viscoelastic relaxation of the capping layer. The stress induced in the channel by the spacer and polysilicon after capping layer etch is nonuniform with maxima near the edges of the gate. Supplementary micro-Raman measurements of SMT test structures and electrical measurements of fabricated SMT devices are consistent with the simulation results. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3239990]