Three level stacked Si nanowires transistors with HfO2/TiN/poly-Si gate all around stacks (transistors called hereafter 3NWG) were processed, thanks to a self-aligned process. A current gain of 4.3 for NMOS and 4.7 for PMOS compared to planar SOI was demonstrated for V-D = 1.2 V and V-G - V-T = 0.8 V, thanks to a 3D integration scheme (stacked and aligned nanowires). Those 3NWG devices revealed a current gain of 4.9 for NMOS and 4.2 for PMOS for V-D = 50 mV when getting rid of the access resistance impact. Thanks to capacitance measurements, we found an expected inversion charge gain per plan-view surface of 6.4, highlighting the potentiality of the 3NWG device. The split-CV technique was used to extract electron and hole effective mobilities. The transport in 3NWG (oil etched surfaces) was compared to the one in planar SOI devices. (c) 2007 Elsevier Ltd. All rights reserved.