For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V, self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 mu m partially-depleted SOI CMOS technology, the static power consumption at 200 degrees C is reduced by nearly three orders of magnitude at the expense of increased delay and area. (C) 2008 Elsevier Ltd. All rights reserved.