The gate and subthreshold drain leakage currents are investigated experimentally in triple-gate FinFETs for power supply voltage V-dd = 1 V. The gate and drain leakage currents are analyzed in terms of the fin width and gate length to clarify their origin. In wide FinFETs, the measured subthreshold drain current is much larger than the gate tunneling current due to the short-channel effects. In narrow FinFETs with negligible short-channel effects, the importance of the trap-assisted sidewall-gate edge tunneling current on the drain leakage current has been demonstrated. This leakage current behavior with decreasing the fin width has been attributed to the higher sidewall-gate interface trap density compared to the top-gate interface trap density. (C) 2009 Elsevier Ltd. All rights reserved.