Threshold voltage (V-T) and drive current (I-ON) variability of low stand-by power (LSTP)-32 nm FinFETs subject to fin line-edge roughness (LER) is investigated through Technology Computer-Aided Design (TCAD) simulations featuring quantum-corrected hydrodynamic transport. Statistical results provided by an ensemble Monte Carlo (MC) approach highlight an increase in the average V-T and a decrease in the average I-ON with respect to sensitivity analysis based predictions. Correlations of fin shape fluctuations to electrical performance are investigated, thus assessing further limitations of sensitivity analysis and proposing better alternatives to the expensive MC approach. An equivalent fin width is calculated, which allows reducing the spread in I-ON scatter plots and highlights relative importance of LER in different fin regions. Simplified device instances with linearly varying fin width are simulated to better assess the impact of local thinning/thickening in the channel, source and drain extensions. Asymmetries in the device behavior are observed upon swapping the taper direction and the critical role of extensions is identified. Moreover, the impact of LER on noise margins of FinFET-based Static Random Access Memories (SRAMs) is investigated, considering the hold, read and write operating modes. Results are compared to published data on fabricated cells with similar device features. "mu - 6 sigma" statistics extracted from 1000 mixed-mode Simulations helps with assessing variability concerns for mainstream integration of aggressively scaled of FinFET-SRAMs. (C) 2009 Elsevier Ltd. All rights reserved.