화학공학소재연구정보센터
Solid-State Electronics, Vol.54, No.2, 205-212, 2010
Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction
We present the fabrication and characterization of Fully-Depleted pMOSFETs processed oil ultra-thin GeOl (Germanium-On-Insulator) wafers obtained by the Enrichment technique The fabrication procedures for wafers and pMOSFETs are detailed The Influence of temperature (77 K < T < 300 K) on front (Ge-high-k) and back (Ge-SiO2 channel properties, such as the hole mobility, the threshold voltage and the substhreshold swing, is reported Very high values of hole mobility have been measured (350 and 595 cm(2) V-1 s(-1) at 300 K and 77 K, respectively) The carrier scattering mechanisms are revealed from the temperature-dependent hole mobility. The role of the interface defects and residual body doping on the parasitic conduction is clarified based on the threshold voltage shift measured at low temperature. An appropriate V-T(T) model, providing relevant information on the D-n distribution in the Ge band gap, is proposed (C) 2009 Elsevier Ltd. All rights reserved.