Vertical interconnects pose an interesting method for heterogeneous integration of electronic technologies allowing three-dimensional (3D) stacking of microelectromechanical systems devices and integrated circuit components. The vertical interconnects, referred to as through-silicon vias, begin with the formation of blind vias in silicon that are eventually exposed by mechanically lapping and polishing the wafer back side. Inductively coupled plasma (ICP) etching using SF6/O-2 gas chemistry at cryogenic temperatures has been investigated as a way to form vias with a tapered sidewall. The point in creating a controlled taper is so that subsequent thin films can be deposited along the sloped sidewall that line the via with insulation, barrier, and seed films. This tapering is necessary if the via lining processes do not provide adequate conformal coverage, a common problem for conventional low temperature deposition processes. In our process for lining the via sidewall, plasma enhanced chemical vapor deposited silicon dioxide is used to insulate vias from the surrounding silicon. Both Ti and Cu are sputter deposited and provide protection from copper migration and a seed film for Cu electrodeposition, respectively. After etching and lining, the vias are filled by reverse pulse plating of Cu. Vias are 20-25 mu m in diameter and etched using different masking materials. The effect of changing gas flow rates, chamber pressure, ICP power, and substrate temperature on etch rate, via profile, and sidewall morphology will be presented. These parameters are critical in the optimization of an etch process for vias of specific dimensions to be used in 3D integration. (C) 2010 American Vacuum Society [DOI: 10.1116/1.3281005]