This work reports on a comprehensive process of trapping centers in Silicon nanocrystal (nc-Si) memories devices. The trap centers have been studied using Random Telegraph Signal (RTS) and Low Frequency (LF) techniques. The study of the traps which are responsible for RTS noise in non-volatile memories (NVM) devices as a function of gate voltage and temperature, offers the opportunity of studying the trapping/detrapping behaviour of a single interface trap center. The RTS parameters of the devices having random discrete fluctuations in the drain current get more information about trap energy level and spatial localization from the SiO2/Si interface. The impact of trap centers has been also investigated showing the significant noise between memories and references devices. Furthermore, it has convincingly been shown that this discrete switching of the drain current between a high and a low state is the basic feature responsible for 1/f(Y) flicker noise in MOSFETs transistors. (C) 2010 Elsevier Ltd. All rights reserved.