Low temperature epitaxy (LTE) in Chemical Vapor Deposition (CVD) refers to 350-650 degrees C interval. This temperature range is critical for this process since the thermal and lattice mismatch (or strain relaxation) issues diminish in advanced BiCMOS processing. The modeling of the epitaxy process is a vital task to increase the understanding the growth process and to design any desired device structure. In this study, an empirical model for Si2H6/Ge2H6-based LTE of SiGe is developed and compared with experimental work. The model can predict the number of free sites on Si surface, growth rate of Si and SiGe, and the Ge content at low temperatures. A good agreement between the model and the experimental data is obtained. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.jes113689] All rights reserved.