Tunneling barrier engineered charge trap. ash (TBE-CTF) memory devices were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin SiO(2) and Si(3)N(4) dielectric layers were used as engineered tunneling barrier. A faster program/erase speed as well as a larger memory window was achieved from the TBE-CTF memory. The VARIOT-type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed a longer retention time and superior endurance characteristic. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at the tunneling barrier/silicon channel by programming and erasing (P/E) stress. (C) 2009 Elsevier B.V. All rights reserved.