A new 3-D stacked NAND flash memory was proposed and key characteristics of the memory were investigated using extensive device simulation. To simplify gate stack etch process, Si/SiGe selective etch process was adopted. By applying silicon trench etch process, threshold voltage (V-TH) variation in a bitline can be reduced and the number of vertical control-gate (CG) stacks can be increased as a result. In the trench between CG stacks, gate stack, poly-Si bodies, back-side oxide (BOX) and shield layer are formed. The 3-D stacked NAND flash memory structure without shield layer showed significant crosstalk between adjacent bodies. By adopting shield layers in the trenches, the cross-talks were completely removed. We designed BOX thickness which guarantees reasonable DIBL (Drain-Induced-Barrier-Lowering) and SS (Sub-threshold Swing). The VTH shift of similar to 1.8 V was observed with the Q(nit) of 6 x 10(12) cm(-2). (C) 2011 Elsevier B. V. All rights reserved.