| 학회 | 한국재료학회 |
| 학술대회 | 2011년 가을 (10/27 ~ 10/29, 신라대학교) |
| 권호 | 17권 2호 |
| 발표분야 | B. Nanomaterials and Processing Technology(나노소재기술) |
| 제목 | Effect of Strain and Band Offset on Memory Margin of Capacitor-less Memory-cell on Strained Si on Relaxed SiGe Layer-on-insulator |
| 초록 | The demand for high density, low power and high speed performance has been increasing. In sub 30-nm DRAM technology, it is difficult to distinguish between the ‘0’ and ‘1’ logic states due to severe charge leakage of the capacitor caused by the high inner electric field. Also, height of the capacitors is beyond 2μm for 25fF capacitance, it brings about leaning effect between adjacent storage capacitors. To overcome these technical issues, several papers has been reported about memory-cell structure without a storage capacitor. It is called a capacitor-less DRAM or a floating-body-cell (FBC). The capacitor-less memory-cell fabricated on a silicon-on-insulator (SOI) wafer consists of one transistor structure, it stores charge in the silicon body using the floating body effect instead of the storage capacitor. In capacitor-less memory-cell, two states of ‘0’ and ’1’ are distinguished using the threshold voltage (VT) difference induced by the kink effect on the SOI. The band offset effect of the relaxed SiGe layer and the strain effect of the strained silicon layer were simulated on the memory margin of a capacitor-less memory-cell at Ge concentration 15, 25 and 35%. The relaxed SiGe layer of unstrained or strained Si on SiGe-on-insulator (SGOI) capacitor-less memory-cell was used to confine holes into the valence band well formed by the valence band offset between silicon and SiGe layer. As lowering potential barrier by hole confinement, floating body effect (FBE) is increased. Moreover, increased mobility by the strain effect in the strained Si channel leads more impact ionization. Ultimately, the memory margin is enhanced by band offset and strain effect. For Ge concentration 35 at%, the memory margin of unstrained Si SGOI cell (band offset effect), strained Si on-insulator (sSOI) cell (strain effect) and strained Si SGOI cell (both effects of band offset and strain) compared with reference SOI capacitor-less memory-cell were increased 4.7, 50.6 and 57.9%, respectively. The possibility of multi-level operation from the large memory margin which results from a capacitor-less memory-cell of the strained Si grown on SGOI is demonstrated. *This work was supported by the IT R&D program of MKE/KEIT. [KI002083 , Next-Generation Substrate Technology for High Performance Semiconductor Devices] |
| 저자 | Seung-Hyun Song1, Du-Yeong Lee2, Sung-Gwang Kim1, Tae-Hyun Kim2, Okuyama Ryosuke1, Tae-Hun Shim2, Jae-Gun Park1 |
| 소속 | 1Advanced Semiconductor Material and Device Development Center, 2Hanyang Univ. |
| 키워드 | 1T-DRAM; strain; SOI; SGOI; cap-less |
