| 학회 | 한국재료학회 |
| 학술대회 | 2017년 봄 (05/17 ~ 05/19, 목포 현대호텔) |
| 권호 | 23권 1호 |
| 발표분야 | A. 전자/반도체 재료 분과 |
| 제목 | Comparative Study on the Electrical Characteristics between Gate-First and Gate-Last Like Processed MOS Devices |
| 초록 | The electrical properties of gate-first and gate-last like processed MOS device structure with HfO2/TiN gate stack has been studied in terms of equivalent oxide thickness (EOT), flatband voltage (VFB), gate leakage current (Jg) and stress induced charge trapping behavior. Compared to high thermal processed device, thinner EOT, higher VFB and a slight higher charge trapping behaviors are observed with low temperature processed device. Some degradation in hysteresis analysis is obtained with low temperature processed device. Thanks to small amount of [Vo2+] within high-k gate dielectric as a result of low temperature processing steps to fabricate MOS devices, improved charge trapping characteristics are observed. Based on our findings, maximum process temperature subtantially affects the electrical characteristics of MOS devices with high-k gate dielectric and metal gate structure. [Acknowledgement] This study was supported by the Future Semiconductor Device Technology Development Program (10044842) funded by MOTIE (Ministry of Trade, Industry & Energy) and KSRC (Korea Semiconductor Research Consortium) as well as the Industrial Technology Innovation Program (10054882, Development of dry cleaning technology for nanoscale patterns) funded by the Ministry of Trade, Industry and Energy (MOTIE, Republic of Korea) |
| 저자 | Hoon Hee Han1, Donghwan Lim2, Yu-Rim Jeon1, Jae Ho Lee2, Changhwan Choi1 |
| 소속 | 1Division of Materials Science and Engineering, 2Hanyang Univ. |
| 키워드 | <P>Flat band voltage; Charge trapping; Oxygen vacancy</P> |
