| 학회 | 한국재료학회 |
| 학술대회 | 2021년 가을 (11/24 ~ 11/26, 경주 라한호텔) |
| 권호 | 27권 2호 |
| 발표분야 | A. 전자/반도체 재료 분과 |
| 제목 | A Study on the Characteristics of wafer Edge Defects |
| 초록 | Recently, with the development of semiconductor and electronic industries, the use of silicon wafers is rapidly increasing. The design rules of the semiconductor process are becoming more and miniaturized, and the defects of the silicon wafer must also be managed very importantly to cause defects in the manufacturing process of the semiconductor device. In case of silicon wafer surface defects, studies have been conducted through many analysis equipment from the past to the present and micro-defects of several nm are currently being managed. However, for defects on the edge of the wafer, there are still areas where many studies have not been conducted in preparation for surface defects. As a result of analyzing the edge defects of polished wafers, particle, scratch and pit defects are mostly observed in wafer edge defects similar to surface defects. Also, unlike surface defects, defects with a rough surface shape are observed depending on the specific edge region and crystal orientation. When checking the properties of each edge defect, it was confirmed that each defect was generated in a specific process or removed in a specific process. The edge defects observed on polished wafer are transferred to a similar shape after EPI growth, and some defects are transferred to EPI stacking fault defects. Also, in EPI wafers defects, other than the defects with the rough surface shape found in the polished wafer, other defects with specific patterns ware confirmed. As a result of the attribute analysis on the pattern defect type, it is estimated that the topology is abnormal growth according to the EPI growth rate. In addition, for these defects, the influence of the device process was identified and the residue phenomenon by PR coating was indirectly evaluated, and it was evaluated as having no significant influence. As such, in the study, the properties and causes of edge defects observed in polished wafers and EPI wafer estimated, and influence of some defects was indirectly confirmed through device process evaluation. |
| 저자 | 신정원 |
| 소속 | SK실트론 |
| 키워드 | <P>Polished wafer; EPI wafer; Edge defect</P> |
