| 학회 |
한국재료학회 |
| 학술대회 |
2003년 가을 (11/21 ~ 11/22, 연세대학교) |
| 권호 |
9권 2호 |
| 발표분야 |
반도체 |
| 제목 |
초미세 메모리 커패시터의 전극형성을 위한 식각 기술 |
| 초록 |
This paper describes some of the key issues associated with the patterning of metal electrodes of sub-micron (especially at the critical dimension (CD) of 0.15 μm) dynamic random access memory (DRAM) devices. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 μm and thus the storage node electrode with the CD of 0.15 μm could not be fabricated using the Pt electrodes. Accordingly, we have proposed novel techniques to surmount the above difficulties. The Ru electrode for the stack-type structure is introduced and alternative schemes based on the introduction of the concave-type structure using Pt or Ru as an electrode material are outlined. |
| 저자 |
김현우 |
| 소속 |
인하대 |
| 키워드 |
Platinum; Ruthenium; Etching; Critical dimension; ractive ion etching lag
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| E-Mail |
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