| 학회 | 한국재료학회 |
| 학술대회 | 2004년 가을 (11/05 ~ 11/05, 인하대학교) |
| 권호 | 10권 2호 |
| 발표분야 | 세라믹스 |
| 제목 | n형 실리콘 기판 기반으로 준비한 Bi3.25La0.75Ti3O12 강유전체 전계 트렌지스터의 기판 의존성 및 유전층 두께 축소에 관한 연구 |
| 초록 | 1. Introduction Ferroelectric-gated field effect transistors (FeFETs) are currently receiving increasing attentions for future nonvolatile ferroelectric random access memory applications since they obey the scaling rule, require low power consumptions and have the advantage over conventional capacitor-type FeRAMs for high-density implementation. As the gate material in a FeFET, the polarization states of the ferroelectric film greatly modifies the magnitude of the source-to-drain current. The current value can be sensed directly without switching the device, permitting a nondestructive read-out of the stored information. Such properties are reliable to thickness of the insulator and the types of substrates used. We report a systematic study of FeFETs using Bi3.25La0.75Ti3O12 on top of an oxidized Si substrate (n-type and p-type) and discuss the effects of substrate difference and scaling of the SiO2 layer. 2. Experimental Prime-grade n-type and p-type Si(100) wafers were purchased and sliced into square pieces with a size of 5×5 mm2, following a standard RCA preparation method. The SiO2 insulating layer was thermally oxidized in a high-temperature furnace at 800℃ and ferroelectric BLT films with 200nm thickness were prepared on by the pulsed laser deposition method (λ=248nm). Deposition was carried out at 400℃ with a deposition pressure of 200mTorr and post-annealing treatments were done for 1hr in an external furnace at a temperature of 650℃. Custom designed Rigaku 8kW rotating anode x-ray generator was used to measure the time dependent thicknesses of these SiO2 films. Thermally evaporated Au dots of size 1.77×10-4cm2 were finally deposited for the top electrode to form a metal-insulator-semiconductor-structure. Electrical properties for both structures were characterized from capacitance-voltage (C-V) and current-voltage (I-V) measurements, extracted by an HP4194A impedance analyzer and a Keithley 617, respectively. 3. Discussions The SiO2 films revealed a thickness of 8nm and 15nm at oxidation periods of 30mins and 60mins. For FeFETs with 15nm SiO2 layers grown on p-type Si substrates, we can observe an ideal C-V hysteresis curve. However, these results from n-type substrates showed an inverted hysteresis, mainly due to different carrier-types. In realizing the FeFETs on n-type substrates, we have focused on scaling the thickness of the SiO2 insulator layer. The C-V curves at various frequencies were stable without any shifts of the flatband voltages. The memory window values for 8nm-FeFETs were extracted to be 0.3V, 2.5V, 5.0V and 7.0Vs at bias voltages of ±5V, ±7V, ±10V, and ±12V, respectively. |
| 저자 | 박재문, 고은정, 남광우, 박광서 |
| 소속 | 서강대 |
| 키워드 | 강유전체 전계 트렌지스터; BLT 박막; 산화실리콘 기판 |
