| 초록 |
Continuing improvement of very large scale integration of microelectronic circuits has reached the point where multilayer metallization and the interlayer dielectric have become the limiting factors in process integration and device performance. The major improvements in performance of microelectronics come from device size miniaturization, which leads to faster device speeds, higher device packing density, and more functions on a chip. As the devices scale to smaller feature sizes, the transistor capacitance and resistance are reduced, yet the line-to-line capacitance and resistance of the metal lines increase. As a result, the resistance-capacitance delay caused by interconnect tends to limit the chip performance. A new generation of low dielectric constant materials is required to achieve the advantages in high speed, low power dissipation, and low cross talk noise. By the year 2001 the minimum feature size will be 0.15, which requires insulation with a dielectric material a dielectric constant =2.3.1 An very low dielectric material will be necessary for the integrated circuits generations after that. Current research on low dielectric constant materials is intensive.At present, several low materials are available from various materials suppliers. However, none is capable of meeting all the requirement.We introduced the perturbed hard-sphere chain (PHSC) equation of state for binary copolymer system to generate nanosize pores in polymer films in order to decrease the density and the dielectric constant of the film.Consider a binary homopolymer / copolymer system where the homopolymer consists of segments A and the copolymer consists of segments B and C. These pores are fabricated by phase separations induced by interaction of more than two polymer segment. The microphase separation transition is known to be controlled by the composition of component and temperature.
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