| 초록 |
Metal-oxide resistive memristor has risen rapidly as a strong candidate for future nonvolatile random access memory. Previously, we demonstrated the unipolar switching feature through Si-phase in the silicon oxide (SiOx) metrix in diverse junction structure with ~107 on/off ratio, nanosecond switching speed, and nanoscale switching filament[1-3]. However, the device commonly has a relatively high programming voltage and is inherent in the uncertainty of the switching in the nanosecond operating, resulting in the reduction of the switching reliability and the increase of the energy consumption for the completion of the switching. Here, we proposed a novel approach to improve the switching performance and the reliability by using an integrated junction structure composing of the SiOx memristor and the graphene barristor in a vertical architecture form. In graphene barristor, a gate bias can effectively change the height of a Schottky barrier formed at a graphene/semiconductor heterojunction by varying graphene’s Fermi level, so that it controls total amount of current through that junction[4]. Under a positive gate bias, the Schottky barrier is lowered, then the switching transition can be occurred at the lower programming voltage. We found that the forming voltage and programming voltage is decreased at positive gate bias. In addition, a high reliability of nanosecond switching operating is achieved. Finally, We present the feasibility of a logic application through a universal gate(NOT, NOR and NAND gate) consisting of the gate tunable SiOx memristors. Our novel approach can provide a simple way to enhance the switching performance of the SiOx memristor. |
