| 학회 | 한국재료학회 |
| 학술대회 | 2008년 봄 (05/22 ~ 05/23, 상록리조트) |
| 권호 | 14권 1호 |
| 발표분야 | 반도체재료 |
| 제목 | CMOS SCALING AND GATE STACK TECHNOLOGY PROGRESS |
| 초록 | In this presentation, efforts to extend the lifetime of CMOS technology will be reviewed along with impact on device performance and reliability. After 30 years of aggressive downsizing of transistors, geometrical scaling has clearly reached fundamental material limits, and is now in the era where further scaling can be realized mainly by new materials and/or device architecture. Traditional gate stacks based on SiO2 and poly-Si are now being replaced by high-k and metal gates. Strain engineering by means of SiGe in source-drain regions along with stress inducing layers are options being practiced since 90nm generation to boost mobility in the channels. New approaches to form low resistance ultra-shallow junctions with high active dopant concentrations are under investigation and likely to be employed in the next generation devices. Options to reduce barrier height of source-drain contacts are also under evaluation. All these options require integration of novel material systems on to a traditional Si platform, and are challenging from an implementation and reliability perspective. The near term approach to extend CMOS lifetime is to import new gate stack materials such as high-k dielectrics and metal gate electrodes in to traditional CMOS device structures. Recent reports show that the major technical issues impeding the implementation of alternative gate stack materials have been solved. In this presentation, major process and integration approaches and issues will be introduced and the reliability status of the-state-of-the-art devices from this approach will be summarized. |
| 저자 | 최리노 |
| 소속 | 인하대 |
| 키워드 | high-k dielectric; metal gate; CMOS |
