| 초록 |
The combination of the copper & low k dielectric material technology in chip fabrication is the well-known solution to fulfill current market requirements such as high performance device, higher density and lower material cost, but this combination has resulted in a weakness in reliability (vulnerability to temperature cycle stress testing) because of the weak mechanical properties of current low k dielectric materials. The obvious CTE mismatch between the low k dielectric layer and other layers in the chip structure results in interlayer chip delamination and chip cracking during temperature cycle testing. The objective of this study is to investigate how to characterize and thereby select optimal packaging solution, especially such as material and process to minimize the vulnerability of the copper/Low k chip, by limiting stress degradation of the chip integrity. By characterization of thermo-mechanical properties of materials and process parameters, we have arrived at a robust packaging solution for copper/ low k devices with improved processing capability, and resultant stable reliability. |
