| 초록 |
This paper demonstrates, for the first time, wafer-scale graphene/MoS2 heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors and logic gates. The short vertical channel of the transistor is formed by sandwiching bulk MoS2 between the bottom indium tin oxide (ITO, drain electrode) and the top graphene (source electrode). The electron injection barriers at the graphene-MoS2 junction and ITO-MoS2 junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The large-area synthesis, transfer, and patterning processes of both semiconducting MoS2 and metallic graphene facilitate construction of a wafer-scale array of transistors and logic gates such as NOT, NAND, and NOR. |
