| 초록 |
We present nonvolatile IGZO transistor memories that contain an ion gel electrolyte as the gate dielectric. Employing ion gel electrolyte led the device to operate at voltages below 10 V, due to the formation of electrical double layers (EDLs). As the charge trapping layer, micro-patches of metals were inserted between the IGZO channel and the ion gel gate dielectric layer. The gate-induced charges in the IGZO channel could be trapped into or detrapped from the inserted metal micro-patches. This results in changes in the electrical environment around the channel and the device current level that corresponds to the programmed or erased signal states of the memory devices. In this study, the type and the density of the micro-patches were controlled to yield optimal performance of the memories, including the programming/erasing voltages and signal retention time. |
