검색결과 : 18건
| No. | Article |
|---|---|
| 1 |
Probing buried interfaces on Ge-based metal gate/high-k stacks by hard X-ray photoelectron spectroscopy Rubio-Zuazo J, Martinez E, Batude P, Clavelier L, Chabli A, Castro GR Applied Surface Science, 257(7), 3007, 2011 |
| 2 |
Growth of InAs/GaAs quantum dots on Si, Ge/Si and germanium-on-insulator-on-silicon (GeOI) substrates emitting in the 1.3 mu m band for silicon photonics Rajesh M, Bordel D, Kawaguchi K, Faure S, Nishioka M, Augendre E, Clavelier L, Guimard D, Arakawa Y Journal of Crystal Growth, 315(1), 114, 2011 |
| 3 |
Direct Bonding of Silicon to Platinum Dargent L, Bogumilowicz Y, Renault O, Ghyselen B, Madar R, Clavelier L Journal of the Electrochemical Society, 158(3), H255, 2011 |
| 4 |
200 mm Silicon On Porous Layer Substrates Made by the Smart Cut Technology for Double Layer-Transfer Applications Stragier AS, Signamarcheix T, Salvetat T, Nolot E, Dechamp J, Mercier D, Gergaud P, Tauzin A, Clavelier L, Lemiti M Journal of the Electrochemical Society, 158(5), H595, 2011 |
| 5 |
An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization Di Cioccio L, Gueguen P, Taibi R, Landru D, Gaudin G, Chappaz C, Rieutord F, de Crecy F, Radu I, Chapelon LL, Clavelier L Journal of the Electrochemical Society, 158(6), P81, 2011 |
| 6 |
Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies Signamarcheix T, Andrieu F, Biasse B, Casse M, Papon AM, Nolot E, Ghyselen B, Faynot O, Clavelier L Solid-State Electronics, 59(1), 8, 2011 |
| 7 |
Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise Valenza M, Gyani J, Martinez F, Soliveres S, Le Royer C, Augendre E, Clavelier L Solid-State Electronics, 59(1), 34, 2011 |
| 8 |
Germanium and Silicon: A Comparative Study of Hydrogenated Interstitial and Vacancy Defects by IR Spectroscopy Rochat N, Tauzin A, Mazen F, Clavelier L Electrochemical and Solid State Letters, 13(5), G40, 2010 |
| 9 |
Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut (TM) technology Widiez J, Rabarot M, Saada S, Mazellier JP, Dechamp J, Delaye V, Roussin JC, Andrieu F, Faynot O, Deleonibus S, Bergonzo P, Clavelier L Solid-State Electronics, 54(2), 158, 2010 |
| 10 |
Schottky Barrier Height Extraction in Ohmic Regime: Contacts on Fully Processed GeOI Substrates Hutin L, Le Royer C, Tabone C, Delaye V, Nemouchi F, Aussenac F, Clavelier L, Vinet M Journal of the Electrochemical Society, 156(7), H522, 2009 |