| 1 |
Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell
Xu ZZ, Liu DH, Hu J, Chen WJ, Qian WS, Kong WR, Zou SC
Solid-State Electronics, 152, 46, 2019 |
| 2 |
An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models
Pereira ASN, de Steel G, Planes N, Haond M, Giacomini R, Flandre D, Kilchytska V
Solid-State Electronics, 128, 67, 2017 |
| 3 |
A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects
Raksharam, Dutta AK
Solid-State Electronics, 130, 33, 2017 |
| 4 |
Behavior of subthreshold conduction in junctionless transistors
Park SJ, Jeon DY, Montes L, Mouis M, Barraud S, Kim GT, Ghibaudo G
Solid-State Electronics, 124, 58, 2016 |
| 5 |
A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer
Liaw YG, Liao WS, Wang MC, Lin CL, Zhou B, Gu HS, Li DS, Zou XC
Solid-State Electronics, 126, 46, 2016 |
| 6 |
A novel scaling theory for fully depleted pi-gate (Pi G) MOSFETs
Chiang TK
Solid-State Electronics, 103, 199, 2015 |
| 7 |
A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) UTB SOI MOSFETs including substrate induced surface potential effectsd
Kumar A, Tiwari PK
Solid-State Electronics, 95, 52, 2014 |
| 8 |
Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs
Wang XS, Brown AR, Cheng BJ, Roy S, Asenov A
Solid-State Electronics, 98, 99, 2014 |
| 9 |
Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime
Jazaeri F, Barbut L, Koukab A, Sallese JM
Solid-State Electronics, 82, 103, 2013 |
| 10 |
Impact of quantum effects on the short channel effects of III-V nMOSFETs in weak and strong inversion regimes
Dutta T, Rafhay Q, Clerc R, Lacord J, Monfray S, Pananakakis G, Boeuf F, Ghibaudo G
Solid-State Electronics, 88, 43, 2013 |
