검색결과 : 9건
| No. | Article |
|---|---|
| 1 |
Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology Fenouillet-Beranger C, Perreau P, Benoist T, Richier C, Haendler S, Pradelle J, Bustos J, Brun P, Tosti L, Weber O, Andrieu F, Orlando B, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gregoire M, Ducote J, Gouraud P, Margain A, Borowiak C, Bianchini R, Planes N, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Boeuf F Solid-State Electronics, 88, 15, 2013 |
| 2 |
Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances Ben Akkez I, Fenouillet-Beranger C, Cros A, Perreau P, Haendler S, Weber O, Andrieu F, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gouraud P, Margain A, Borowiak C, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Balestra F, Ghibaudo G, Boeuf F Solid-State Electronics, 90, 143, 2013 |
| 3 |
Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology Fenouillet-Beranger C, Perreau P, Boulenc P, Tosti L, Barnola S, Andrieu F, Weber O, Beneyton R, Perrot C, de Buttet C, Abbate F, Campidelli Y, Pinzelli L, Gouraud P, Margain A, Peru S, Bourdelle KK, Nguyen BY, Boedt F, Poiroux T, Faynot O, Skotnicki T, Boeuf F Solid-State Electronics, 74, 32, 2012 |
| 4 |
Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below Fenouillet-Beranger C, Perreau P, Denorme S, Tosti L, Andrieu F, Weber O, Monfray S, Barnola S, Arvet C, Campidelli Y, Haendler S, Beneyton R, Perrot C, de Buttet C, Gros P, Pham-Nguyen L, Leverd F, Gouraud P, Abbate F, Baron F, Torres A, Laviron C, Pinzelli L, Vetier J, Borowiak C, Margain A, Delprat D, Boedt F, Bourdelle K, Nguyen BY, Faynot O, Skotnicki T Solid-State Electronics, 54(9), 849, 2010 |
| 5 |
Gate-all-around technology: Taking advantage of ballistic transport? Huguenin JL, Bidal G, Denorme S, Fleury D, Loubet N, Pouydebasque A, Perreau P, Leverd F, Barnola S, Beneyton R, Orlando B, Gouraud P, Salvetat T, Clement L, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 54(9), 883, 2010 |
| 6 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |
| 7 |
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution Bidal G, Loubet N, Fenouillet-Beranger C, Denorme S, Perreau P, Fleury D, Clement L, Laviron C, Leverd F, Gouraud P, Barnola S, Beneyton R, Torres A, Duluard C, Chapon JD, Orlando B, Salvetat T, Grosjean M, Deloffre E, Pantel R, Dutartre D, Monfray S, Ghibaudo G, Boeuf F, Skotnicki T Solid-State Electronics, 53(7), 735, 2009 |
| 8 |
65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications Tavel B, Duriez B, Gwoziecki R, Basso MT, Julien C, Ortolland C, Laplanche Y, Fox R, Sabouret E, Detcheverry C, Boeuf F, Morin P, Barge D, Bidaud M, Bienacel J, Garnier P, Cooper K, Chapon JD, Trouiller Y, Belledent J, Broekaart M, Gouraud P, Denais M, Huard V, Rochereau K, Difrenza R, Planes N, Marin M, Boret S, Gloria D, Vanbergue S, Abramowitz P, Vishnubhotla L, Reber D, Stolk P, Woo M, Arnaud F Solid-State Electronics, 50(4), 573, 2006 |
| 9 |
A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates Muller M, Mondot A, Aime D, Froment B, Talbot A, Roux JM, Ribes G, Morand Y, Descombes S, Gouraud P, Leverd F, Pokrant S, Toffoli A, Skotnicki T Solid-State Electronics, 50(4), 620, 2006 |