검색결과 : 24건
| No. | Article |
|---|---|
| 1 |
The defect-centric perspective of device and circuit reliability-From gate oxide defects to circuits Kaczer B, Franco J, Weckx P, Roussel PJ, Simicic M, Putcha V, Bury E, Cho M, Degraeve R, Linten D, Groeseneken G, Debacker P, Parvais B, Raghavan P, Catthoor F, Rzepa G, Waltl M, Goes W, Grasser T Solid-State Electronics, 125, 52, 2016 |
| 2 |
Stack optimization of oxide-based RRAM for fast write speed (< 1 mu s) at low operating current (< 10 mu A) Chen CY, Goux L, Fantini A, Degraeve R, Redolfi A, Groeseneken G, Jurczak M Solid-State Electronics, 125, 198, 2016 |
| 3 |
Analysis of slow de-trapping phenomena after a positive gate bias on AlGaN/GaN MIS-HEMTs with in-situ Si3N4/Al2O3 bilayer gate dielectrics Wu TL, Marcon D, Ronchi N, Bakeroot B, You SZ, Stoffels S, Van Hove M, Bisi D, Meneghini M, Groeseneken G, Decoutere S Solid-State Electronics, 103, 127, 2015 |
| 4 |
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, Loo R, Groeseneken G, Huyghebaert C Solid-State Electronics, 83, 50, 2013 |
| 5 |
Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks Ritzenthaler R, Schram T, Bury E, Spessot A, Caillat C, Srividya V, Sebaai F, Mitard J, Ragnarsson LA, Groeseneken G, Horiguchi N, Fazan P, Thean A Solid-State Electronics, 84, 22, 2013 |
| 6 |
Modeling the impact of junction angles in tunnel field-effect transistors Kao KH, Verhulst AS, Vandenberghe WG, Soree B, Groeseneken G, De Meyer K Solid-State Electronics, 69, 31, 2012 |
| 7 |
Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs Vandooren A, Leonelli D, Rooyackers R, Arstila K, Groeseneken G, Huyghebaert C Solid-State Electronics, 72, 82, 2012 |
| 8 |
Study of nitrogen impact on V-FB-EOT roll-off by varying interfacial SiO2 thickness Cho M, Akheyar A, Aoulaiche M, Degraeve R, Ragnarsson LA, Tseng J, Hoffmann TY, Groeseneken G Solid-State Electronics, 62(1), 67, 2011 |
| 9 |
Advanced PBTI reliability with 0.69 nm EOT GdHfO gate dielectric Cho M, Aoulaiche M, Degraeve R, Kaczer B, Kauerauf T, Ragnarsson LA, Adelmann C, Van Elshocht S, Hoffmann TY, Groeseneken G Solid-State Electronics, 63(1), 5, 2011 |
| 10 |
Drive current enhancement in p-tunnel FETs by optimization of the process conditions Leonelli D, Vandooren A, Rooyackers R, De Gendt S, Heyns MM, Groeseneken G Solid-State Electronics, 65-66, 28, 2011 |