검색결과 : 7건
| No. | Article |
|---|---|
| 1 |
Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation Matsukawa T, Liu YX, Mori T, Morita Y, Otsuka S, O'uchi S, Fuketa H, Migita S, Masahara M Solid-State Electronics, 132, 103, 2017 |
| 2 |
Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors Mizubayashi W, Fukuda K, Mori T, Endo K, Liu YX, Matsukawa T, O'uchi S, Ishikawa Y, Migita S, Morita Y, Tanabe A, Tsukada J, Yamauchi H, Masahara M, Ota H Solid-State Electronics, 111, 62, 2015 |
| 3 |
Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on performance of tunnel field-effect transistors Morita Y, Mori T, Migita S, Mizubayashi W, Fukuda K, Matsukawa T, Endo K, O'uchi S, Liu YX, Masahara M, Ota H Solid-State Electronics, 113, 173, 2015 |
| 4 |
Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model Morita Y, Mori T, Migita S, Mizubayashi W, Tanabe A, Fukuda K, Matsukawa T, Endo K, O'uchi S, Liu YX, Masahara M, Ota H Solid-State Electronics, 102, 82, 2014 |
| 5 |
Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition Endo K, Ishikawa Y, Matsukawa T, Liu YX, O'uchi S, Sakamoto K, Tsukada J, Yamauchi H, Masahara M Solid-State Electronics, 74, 13, 2012 |
| 6 |
Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL) Cho S, Lee JH, O'uchi S, Endo K, Masahara M, Park BG Solid-State Electronics, 54(10), 1060, 2010 |
| 7 |
Dual metal gate FinFET integration by Ta/Mo diffusion technology for V-t reduction and multi-V-t CMOS application Matsukawa T, Endo K, Liu YX, O'uchi S, Ishikawa Y, Yamauchi H, Tsukada J, Ishii K, Sakamoto K, Suzuki E, Masahara M Solid-State Electronics, 53(7), 701, 2009 |