검색결과 : 23건
| No. | Article |
|---|---|
| 1 |
Study of line-TFET analog performance comparing with other TFET and MOSFET architectures Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 128, 43, 2017 |
| 2 |
Staggered band gap n+In0.5Ga0.5As/p + GaAs0.5Sb0.5 Esaki diode investigations for TFET device predictions El Kazzi S, Smets Q, Ezzedini M, Rooyackers R, Verhulst A, Douhard B, Bender H, Collaert N, Merckling C, Heyns MM, Thean A Journal of Crystal Growth, 424, 62, 2015 |
| 3 |
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism Martino MD, Neves F, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 112, 51, 2015 |
| 4 |
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, Loo R, Groeseneken G, Huyghebaert C Solid-State Electronics, 83, 50, 2013 |
| 5 |
Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques Redolfi A, Kubicek S, Rooyackers R, Kim MS, Sleeckx E, Devriendt K, Shamiryan D, Vandeweyer T, Delande T, Horiguchi N, Togo M, Wouters JMD, Jurczak M, Hoffmann T, Cockburn A, Gravey V, Diehl DL Solid-State Electronics, 71, 106, 2012 |
| 6 |
Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs Vandooren A, Leonelli D, Rooyackers R, Arstila K, Groeseneken G, Huyghebaert C Solid-State Electronics, 72, 82, 2012 |
| 7 |
Temperature impact on the tunnel fet off-state current components Agopian PGD, Martino MD, dos Santos SG, Martino JA, Rooyackers R, Leonelli D, Claeys C Solid-State Electronics, 78, 141, 2012 |
| 8 |
Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs Kilchytska V, Alvarado J, Collaert N, Rooyackers R, Put S, Simoen E, Claeys C, Flandre D Solid-State Electronics, 59(1), 18, 2011 |
| 9 |
Drive current enhancement in p-tunnel FETs by optimization of the process conditions Leonelli D, Vandooren A, Rooyackers R, De Gendt S, Heyns MM, Groeseneken G Solid-State Electronics, 65-66, 28, 2011 |
| 10 |
Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering Ferain I, Duffy R, Collaert N, van Dal MJH, Pawlak BJ, O'Sullivan B, Witters L, Rooyackers R, Conard T, Popovici M, van Elshocht S, Kaiser M, Weemaes RGR, Swerts J, Jurczak M, Lander RJP, De Meyer K Solid-State Electronics, 53(7), 760, 2009 |