검색결과 : 28건
| No. | Article |
|---|---|
| 1 |
Gate-based high fidelity spin readout in a CMOS device Urdampilleta M, Niegemann DJ, Chanrion E, Jadot B, Spence C, Mortemousque PA, Bauerle C, Hutin L, Bertrand B, Barraud S, Maurand R, Sanquer M, Jehl X, De Franceschi S, Vinet M, Meunier T Nature Nanotechnology, 14(8), 737, 2019 |
| 2 |
New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures Llorente CD, Colinge JP, Martinie S, Cristoloveanu S, Wan J, Le Royer C, Ghibaudo G, Vinet M Solid-State Electronics, 159, 26, 2019 |
| 3 |
Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 159, 83, 2019 |
| 4 |
GDNMOS and GDBIMOS devices for high voltage ESD protection in thin film advanced FD-SOI technology De Conti L, Bedecarrats T, Cristoloveanu S, Vinet M, Galy P Solid-State Electronics, 159, 90, 2019 |
| 5 |
New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube (TM) integration Llorente CD, Le Royer C, Batude P, Fenouillet-Beranger C, Martinie S, Lu CMV, Allain F, Colinge JP, Cristoloveanu S, Ghibaudo G, Vinet M Solid-State Electronics, 144, 78, 2018 |
| 6 |
Electrical characterization of vertically stacked p-FET SOI nanowires Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 141, 84, 2018 |
| 7 |
Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 149, 62, 2018 |
| 8 |
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 128, 60, 2017 |
| 9 |
Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations Navarro C, Barraud S, Martinie S, Lacord J, Jaud MA, Vinet M Solid-State Electronics, 128, 155, 2017 |
| 10 |
Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs Hutin L, Oeflein RP, Borrel J, Martinie S, Tabone C, Le Royer C, Vinet M Solid-State Electronics, 115, 160, 2016 |