검색결과 : 7건
| No. | Article |
|---|---|
| 1 |
Comparison of dual-k spacer and single-k spacer for single NWFET and 3-stack NWFET Ko H, Kim J, Kim M, Kang M, Shin H Solid-State Electronics, 140, 64, 2018 |
| 2 |
Investigation and analysis of dual-k spacer with different materials and spacer lengths for nanowire-FET performance Ko H, Kim J, Kang M, Shin H Solid-State Electronics, 136, 68, 2017 |
| 3 |
Analysis and optimization of RC delay in vertical nanoplate FET Woo C, Ko K, Kim J, Kim M, Kang M, Shin H Solid-State Electronics, 136, 81, 2017 |
| 4 |
A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer Liaw YG, Liao WS, Wang MC, Lin CL, Zhou B, Gu HS, Li DS, Zou XC Solid-State Electronics, 126, 46, 2016 |
| 5 |
Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs Yoshida T, Kobayashi K, Otsuji T, Suemitsu T Solid-State Electronics, 102, 93, 2014 |
| 6 |
Doubling speed using strained Si/SiGe CMOS technology Olsen SH, Temple M, O'Neill AG, Paul DJ, Chattopadhyay S, Kwa KSK, Driscoll LS Thin Solid Films, 508(1-2), 338, 2006 |
| 7 |
Response of a sequential-valve-gate system used for thin-wall injection molding Chen SC, Chien RD, Tseng HH, Huang JS Journal of Applied Polymer Science, 98(5), 1969, 2005 |