| 1 |
Device design of single-gated feedback field-effect transistors to achieve latch-up behaviors with high current gains
Woo S, Kim S
Current Applied Physics, 20(10), 1156, 2020 |
| 2 |
ESD robustness concern for SOI-LIGBTs with typical latch-up immunity structures
Ye R, Liu SY, Sun WF, Hou B
Solid-State Electronics, 137, 6, 2017 |
| 3 |
Automatic verification of operating schedules for batch processes using symbolic model checking: Latch model vs. real-time
Kim J, Moon I
Korean Journal of Chemical Engineering, 27(6), 1654, 2010 |
| 4 |
Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors
Carrara F, Presti CD, Scuderi A, Palmisano G
Solid-State Electronics, 54(9), 957, 2010 |
| 5 |
Latch-up effects in CMOS inverters due to high power pulsed electromagnetic interference
Kim K, Iliadis AA
Solid-State Electronics, 52(10), 1589, 2008 |
| 6 |
A new LIGBT structure to suppress substrate currents in a junction isolated technology
Bakeroot B, Doutreloigne J, Moens P
Solid-State Electronics, 49(3), 363, 2005 |
| 7 |
Transient blocking characteristics of highly efficient junction isolations based on standard CMOS process
Starke TKH, Igic PM
Solid-State Electronics, 49(7), 1217, 2005 |
| 8 |
Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI
Kim JI, Kong BS
Current Applied Physics, 4(1), 49, 2004 |
| 9 |
A small sized lateral trench electrode IGBT for improving latch-up and breakdown characteristics
Kang EG, Sung MY
Solid-State Electronics, 46(2), 295, 2002 |
| 10 |
Regulation of shortening velocity by calponin in intact contracting smooth muscles
Takahashi K, Yoshimoto R, Fuchibe K, Fujishige A, Mitsu-Saito M, Hori M, Ozaki H, Yamamura H, Awata N, Taniguchi S, Katsuki M, Tsuchiya T, Karaki H
Biochemical and Biophysical Research Communications, 279(1), 150, 2000 |
