Solid-State Electronics

Solid-State Electronics, Vol.128 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (30 articles)

1 - 2	Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 Sverdlov V, Selberherr S
3 - 9	SOI technology for power management in automotive and industrial applications Stork JMC, Hosey GP
10 - 16	Reliable gate stack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology Mohamad B, Leroux C, Rideau D, Haond M, Reimbold G, Ghibaudo G
17 - 24	Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations Elmessary MA, Nagy D, Aldegunde M, Seoane N, Indalecio G, Lindberg J, Dettmer W, Peric D, Garcia-Loureiro AJ, Kalna K
25 - 30	Variability and self-average of impurity-limited resistance in quasi-one dimensional nanowires Sano N
31 - 36	Drain current local variability from linear to saturation region in 28 nm bulk NMOSFETs Karatsori TA, Theodorou CG, Haendler S, Dimitriadis CA, Ghibaudo G
37 - 42	Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits Strangio S, Palestri P, Lanuzza M, Esseni D, Crupi F, Selmi L
43 - 47	Study of line-TFET analog performance comparing with other TFET and MOSFET architectures Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C
48 - 53	Confinement orientation effects in S/D tunneling Medina-Bailon C, Sampedro C, Gamiz F, Godoy A, Donetti L
54 - 59	Process modules for GeSn nanoelectronics with high Sn-contents Schulte-Braucks C, Glass S, Hofmann E, Stange D, von den Driesch N, Hartmann JM, Ikonic Z, Zhao QT, Buca D, Mantl S
60 - 66	Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA
67 - 71	An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models Pereira ASN, de Steel G, Planes N, Haond M, Giacomini R, Flandre D, Kilchytska V
72 - 79	Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14 nm UTBB FDSOI technology Berthelon R, Andrieu F, Ortolland S, Nicolas R, Poiroux T, Baylac E, Dutartre D, Josse E, Claverie A, Haond M
80 - 86	Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typical conduction mechanisms Park HJ, Pirro L, Czornomaz L, Ionica I, Bawedin M, Djara V, Deshpande V, Cristoloveanu S
87 - 91	DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration Deshpande V, Djara V, O'Connor E, Hashemi P, Balakrishnan K, Caimi D, Sousa M, Czornomaz L, Fompeyrine J
92 - 101	Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements Tomaszewski D, Gluszko G, Lukasiak L, Kucharski K, Malesinska J
102 - 108	Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology Boudier D, Cretu B, Simoen E, Carin R, Veloso A, Collaert N, Thean A
109 - 114	Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part II: Measurements and results Boudier D, Cretu B, Simoen E, Carin R, Veloso A, Collaert N, Thean A
115 - 120	Systematic method for electrical characterization of random telegraph noise in MOSFETs Marquez C, Rodriguez N, Gamiz F, Ohata A
121 - 128	RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers Esfeh BK, Makovejev S, Basso D, Desbonnets E, Kilchytska V, Flandre D, Raskin JP
129 - 134	Numerical investigation of plasma effects in silicon MOSFETs for THz-wave detection Jungemann C, Linn T, Bittner K, Brachtendorf HG
135 - 140	Anisotropic interpolation method of silicon carbide oxidation growth rates for three-dimensional simulation Simonka V, Nawratil G, Hossinger A, Weinbub J, Selberherr S
141 - 147	Framework to model neutral particle flux in convex high aspect ratio structures using one-dimensional radiosity Manstetten P, Filipovic L, Hossinger A, Weinbub J, Selberherr S
148 - 154	Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors Baldauf T, Heinzig A, Trommer J, Mikolajick T, Weber WM
155 - 162	Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations Navarro C, Barraud S, Martinie S, Lacord J, Jaud MA, Vinet M
163 - 171	Simulation study of a novel 3D SPAD pixel in an advanced FD-SOI technology Vignetti MM, Calmon F, Lesieur P, Savoy-Navarro A
172 - 179	Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology Athanasiou S, Legrand CA, Cristoloveanu S, Galy P
180 - 186	Sharp-switching band-modulation back-gated devices in advanced FDSOI technology El Dirani H, Fonteneau P, Solaro Y, Legrand CA, Marin-Cudraz D, Ferrari P, Cristoloveanu S
187 - 193	Electrical characterization and modeling of 1T-1R RRAM arrays with amorphous and poly-crystalline HfO2 Grossi A, Zambelli C, Olivo P, Crespo-Yepes A, Martin-Martinez J, Rodriguez R, Nafria M, Perez E, Wenger C
194 - 199	Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM Takamura Y, Shuto Y, Yamamoto S, Funakubo H, Kurosawa MK, Nakagawa S, Sugahara S