Solid-State Electronics

Solid-State Electronics, Vol.159 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (29 articles)

1 - 2	This special issue is devoted to selected papers presented at the EuroSOI-ULIS2018 international conference, held in Granada, Spain on 19-21 March 2018 Preface Gamiz F, Donetti L, Sampedro C
3 - 11	Doping profile extraction in thin SOI films: Application to A2RAM Wakam FT, Lacord J, Bawedin M, Martinie S, Cristoloveanu S, Ghibaudo G, Barbe JC
12 - 18	Investigation of thin gate-stack Z(2)-FET devices as capacitor-less memory cells Navarro S, Marquez C, Lee KH, Navarro C, Parihar M, Park H, Galy P, Bawedin M, Kim YT, Cristoloveanu S, Gamiz F
19 - 25	A thorough study of Si nanowire FETs with 3D Multi-Subband Ensemble Monte Carlo simulations Donetti L, Sampedro C, Ruiz FG, Godoy A, Gamiz F
26 - 37	New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures Llorente CD, Colinge JP, Martinie S, Cristoloveanu S, Wan J, Le Royer C, Ghibaudo G, Vinet M
38 - 42	TFET inverter static and transient performances in presence of traps and localized strain Gnani E, Visciarelli M, Gnudi A, Reggiani S, Baccarani G
43 - 50	Current and shot noise at spin-dependent hopping through junctions with ferromagnetic contacts Sverdlov V, Selberherr S
51 - 56	Characterization of the interface-driven 1st Reset operation in HfO2-based 1T1R RRAM devices Perez E, Mahadevaiah MK, Zambelli C, Olivo P, Wenger C
57 - 62	A flexible characterization methodology of RRAM: Application to the modeling of the conductivity changes as synaptic weight updates Pedro M, Martin-Martinez J, Rodriguez R, Gonzalez MB, Campabadal F, Nafria M
63 - 70	Ferroelectric properties of SOS and SOI pseudo-MOSFETs with HfO2 interlayers Popov VP, Antonov VA, Ilnitsky MA, Tyschenko IE, Vdovin VI, Miakonkikh AV, Rudenko KV
71 - 76	Transient negative capacitance and charge trapping in FDSOI MOSFETs with ferroelectric HfYOX Han QH, Aleksa P, Tromm TCU, Schubert J, Mantl S, Zhao QT
77 - 82	28 nm FDSOI analog and RF Figures of Merit at N-2 cryogenic temperatures Esfeh BK, Planes N, Haond M, Raskin JP, Flandre D, Kilchytska V
83 - 89	Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA
90 - 98	GDNMOS and GDBIMOS devices for high voltage ESD protection in thin film advanced FD-SOI technology De Conti L, Bedecarrats T, Cristoloveanu S, Vinet M, Galy P
99 - 105	A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models Diaz-Fortuny J, Martin-Martinez J, Rodriguez R, Castro-Lopez R, Roca E, Fernandez FV, Nafria M
106 - 115	Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures Beckers A, Jazaeri F, Bohuslayskyi H, Hutin L, De Franceschi S, Enz C
116 - 122	Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range Pavanello MA, Cerdeira A, Doria RT, Ribeiro TA, Avila-Herrera F, Estrada M
123 - 128	2D and 3D TCAD simulation of III-V channel FETs at the end of scaling Aguirre P, Rau M, Schenk A
129 - 134	Quantum modeling of threshold voltage in Ge dual material gate (DMG) FinFET Saha R, Bhowmick B, Baishya S
135 - 141	Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs Zagni N, Puglisi FM, Pavan P, Verzellesi G
142 - 149	Effect of degree of strain relaxation on polarization charges of GaN/InGaN/GaN hexagonal and triangular nanowire solar cells Routray SR, Lenka TR
150 - 156	Near-field scanning microwave microscope platform based on a coaxial cavity resonator for the characterization of semiconductor structures Bagdad BA, Lozano C, Gamiz F
157 - 164	Comparison of memory effect with voltage or current charging pulse bias in MIS structures based on codoped Si-NCs embedded in SiO2 or HfOx Mazurak A, Mroczynski R
165 - 170	Impact of threshold voltage extraction methods on semiconductor device variability Espinera G, Nagy D, Garcia-Loureiro A, Seoane N, Indalecio G
171 - 176	Experimental analysis and improvement of the DC method for self-heating estimation Mori CAB, Agopian PGD, Martino JA
177 - 183	Investigation of built-in bipolar junction transistor in FD-SOI BIMOS Bedecarrats T, Galy P, Fenouillet-Beranger C, Cristoloveanu S
184 - 190	A new method for characterization of gate overlap capacitances and effective channel size in MOSFETs Tomaszewski D, Gluszko G, Kucharski K, Malesinska J
191 - 196	Analytical modeling of capacitances in tunnel-FETs including the effect of Schottky barrier contacts Farokhnejad A, Schwarz M, Horst F, Iniguez B, Lime F, Kloes A
197 - 203	Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET Sato S, Ghibaudo G, Benea L, Ionica I, Omura Y, Cristoloveanu S