Solid-State Electronics
Solid-State Electronics, Vol.97 Entire volume, number list
ISSN: 0038-1101 (Print)
In this Issue (14 articles)
| 1 - 1 |
SSE Special Issue EuroSOI-2013 Foreword Anghel C, Vladimirescu A |
| 2 - 7 |
SOI dual-gate ISFET with variable oxide capacitance and channel thickness Park JK, Jang HJ, Park JT, Cho WJ |
| 8 - 13 |
Reliability of ultra-thin buried oxides for multi-V-T FDSOI technology Besnard G, Garros X, Nguyen P, Andrieu F, Reynaud P, Van Den Daele W, Bourdelle KK, Schwarzenbach W, Toffoli A, Kies R, Delprat D, Reimbold G, Cristoloveanu S |
| 14 - 22 |
Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics dos Santos SD, Cretu B, Strobel V, Routoure JM, Carin R, Martino JA, Aoulaiche M, Jurczak M, Simoen E, Claeys C |
| 23 - 29 |
Z(2)-FET: A promising FDSOI device for ESD protection Solaro Y, Wan J, Fonteneau P, Fenouillet-Beranger C, Le Royer B, Zaslavsky A, Ferrari P, Cristoloveanu S |
| 30 - 37 |
Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications Sasaki KRA, Nicoletti T, Almeida LM, dos Santos SD, Nissimoff A, Aoulaiche M, Simoen E, Claeys C, Martino JA |
| 38 - 44 |
Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit Arshad MKM, Kilchytska V, Emam M, Andrieu F, Flandre D, Raskin JP |
| 45 - 51 |
Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes Niebojewski H, Le Royer C, Morand Y, Rozeau O, Jaud MA, Dubois E, Poiroux T, Bensahel D |
| 52 - 58 |
On the g(m)/I-D-based approaches for threshold voltage extraction in advanced MOSFETs and their application to ultra-thin body SOI MOSFETs Rudenko T, Arshad MKM, Raskin JP, Nazarov A, Flandre D, Kilchytska V |
| 59 - 65 |
RF losses, crosstalk and temperature dependence for SOI and Si/SiC hybrid substrates Lotfi S, Vestling L, Olsson J |
| 66 - 75 |
Characteristics of GaN and AlGaN/GaN FinFETs Im KS, Kang HS, Lee JH, Chang SJ, Cristoloveanu S, Bawedin M, Lee JH |
| 76 - 81 |
Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm Knoll L, Richter S, Nichau A, Trellenkamp S, Schafer A, Bourdelle KK, Hartmann JM, Zhao QT, Mantl S |
| 82 - 87 |
Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (-2 GPa): From fabrication (Ge enrichment process) to in-depth characterizations Glowacki E, Le Royer C, Morand Y, Pedini JM, Denneulin T, Cooper D, Barnes JP, Nguyen P, Rouchon D, Hartmann JM, Gourhant O, Baylac E, Campidelli Y, Barge D, Bonnin O, Schwarzenbach W |
| 88 - 98 |
Enhanced coupling effects in vertical double-gate FinFETs Chang SJ, Bawedin M, Guo YF, Liu FY, Akarvardar K, Lee JH, Lee JH, Ionica I, Cristoloveanu S |