Solid-State Electronics
Solid-State Electronics, Vol.50, No.1 Entire volume, number list
ISSN: 0038-1101 (Print)
In this Issue (15 articles)
| 1 - 1 |
Solid-State Electronics - Foreword Sangiorgi E, Fiegna C |
| 2 - 9 |
High-performance bulk CMOS technology for 65/45 nm nodes Sugii T |
| 10 - 17 |
Numerical modeling of RF noise in scaled MOS devices Jungemann C, Neinhus B, Nguyen CD, Scholten AJ, Tiemeijer LF, Meinerzhagen B |
| 18 - 23 |
Multigate silicon MOSFETs for 45 nm node and beyond Poiroux T, Vinet M, Faynot O, Widiez J, Lolivier J, Previtali B, Ernst T, Deleonibus S |
| 24 - 31 |
Phase change memories: State-of-the-art, challenges and perspectives Lacaita AL |
| 32 - 37 |
Growth of strained Si on He ion implanted Si/SiGe heterostructures Buca D, Feste SF, Hollander B, Mantl S, Loo R, Caymax M, Carius R, Schaefer H |
| 38 - 43 |
Influence of crystal orientation and body doping on trigate transistor performance Landgraf E, Rosner W, Stadele M, Dreeskornfeld L, Hartwich J, Hofmann F, Kretz J, Lutz T, Luyken RJ, Schulz T, Specht M, Risch L |
| 44 - 51 |
Scaling properties of the tunneling field effect transistor (TFET): Device and circuit Nirschl T, Henzler S, Fischer J, Fulde M, Bargagli-Stoffi A, Sterkel M, Sedlmeir J, Weber C, Heinrich R, Schaper U, Einfeld J, Neubert R, Feldmann U, Stahrenberg K, Ruderer E, Georgakos G, Huber A, Kakoschke R, Hansch W, Schmitt-Landsiedel D |
| 52 - 57 |
Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs Simoen E, Claeys C, Lukyanchikova N, Garbar N, Smolanka A, Der Agopian PG, Martino JA |
| 58 - 62 |
Preparation and characterization of rare earth scandates as alternative gate oxide materials Wagner M, Heeg T, Schubert J, Zhao C, Richard O, Caymax M, Afanas'ev VV, Mantl S |
| 63 - 68 |
Low frequency noise characterization and modelling in ultrathin oxide MOSFETs Contaret T, Romanjek K, Boutchacha T, Ghibaudo G, Boeuf F |
| 69 - 77 |
Analytical model for quantization on strained and unstrained bulk nMOSFET and its impact on quasi-ballistic current Ferrier M, Clerc R, Ghibaudo G, Boeuf F, Skotnicki T |
| 78 - 85 |
Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs Marchi A, Gnani E, Reggiani S, Rudan M, Baccarani G |
| 86 - 93 |
Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15 nm UTB SOI based 6T SRAM operation Samsudin K, Cheng B, Brown AR, Roy S, Asenov A |
| 94 - 101 |
Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation Saint-Martin J, Bournel A, Dollfus P |